林嘉文教授:When Deep Learning Meets IC Fabrication: A Data-Driven Approach to IC Design for Manufacturability
发布时间: 2019-06-28 浏览次数: 3360

报告题目:When Deep Learning Meets IC Fabrication: A Data-Driven Approach to IC Design for Manufacturability

报告人:林嘉文 教授

报告时间:07月10日 15:00

报告地点:912会议室

  

报告人简介:

    林嘉文教授于2000年获台湾清华大学(NTHU)电机工程专业博士学位,现为台湾清华大学电机系教授IEEE Fellow2018 - 2019IEEE电路与系统学会的杰出讲师。研究领域包括图像/视频处理和视频网络。现任NTHU人工智能研究中心副主任,NTHU EECS学院多媒体技术研究中心主任,中国图像处理与模式识别协会台湾地区会长。曾担任Associate Editor of IEEE Transactions on Image Processing, IEEE Transactions on Multimedia, IEEE Transactions on Circuits and Systems for Video Technology, IEEE Multimedia期刊副编辑。还担任了2013-2015年度IEEE Transactions on Multimedia指导委员会成员,及IEEE CASS多媒体系统和应用技术委员会主席;于2010年担任IEEE ICME技术计划联合主席并于2019年担任台北IEEE ICIPTPC主席。他的论文荣获IEEE VCIP 2015最佳论文奖及SPIE VCIP 2005年度青年研究者奖。


报告内容简介:

Traditionally, after ID circuit design and layout, it takes months to fabricate an IC wafer, involving a multiple-step sequence of photolithographic and chemical processing, which can significantly deform the layout patterns and is too complex to model mathematically. Usually we cannot identify defects (e.g., broken wires) of metal wires due to deformations of layout patterns caused by IC fabrication until capturing the scanning electron microscope (SEM) images of fabricated IC wafers, making the circuit design and verification very costly and time-consuming. To address the above problem, there two essential concerns in terms of IC design for manufacturability: (1) How to predict the manufactured IC circuitry from an IC layout so as to assess the layout quality accordingly in a pre-simulation process, and (2) How to automatically modify IC layout patterns so that the manufactured IC circuitry can match the desired patterns as possible. In this talk, we will show how deep-learning-based image prediction can assist IC design for manufacturability. To this end, we formulate the lithography and etching processes of metal layers as a set of nonlinear warping functions between a patch of IC layout pattern and its corresponding SEM image, and models the set of warping functions using a CNN-based LithoNet parametrized with IC fabrication parameters. Based on LithoNet, we also propose a CNN-based OPCNet that can automatically modify an IC layout pattern so that its fabricated IC circuitry well match the desired layout pattern, the so-called Optical Proximity Correction (OPC) process.